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features ? single 3.3v 10% supply fast read access time ? 200 ns automatic page write operation ? internal address and data latches for 128 bytes ? internal control timer fast write cycle time ? page write cycle time ? 10 ms maximum ? 1 to 128-byte page write operation low power dissipation ? 15 ma active current ?20 a cmos standby current hardware and software data protection data polling for end of write detection high reliability cmos technology ? endurance: 100,000k cycles ? data retention: 10 years jedec approved byte-wide pinout commercial, industrial and automotive temperature ranges green (pb/halide-free) packaging option 1. description the at28lv010 is a high-performance 3-volt only electrically erasable and program- mable read-only memory. its 1 megabit of memory is organized as 131,072 words by 8 bits. manufactured with atmel?s advanced nonvolatile cmos technology, the device offers access times to 200 ns with power dissipation of just 54 mw. when the device is deselected, the cmos standby current is less than 20 a. the at28lv010 is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. during a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a write cycle, the device will automatically write the latched data using an internal contro l timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. atmel?s 28lv010 has additional features to ensure high quality and manufacturability. the device utilizes internal error correction for extended endurance and improved data retention characteristics. software dat a protection is implemented to guard against inadvertent writes. the device also includes an extra 128 bytes of eeprom for device identification or tracking. 1-megabit (128k x 8) low voltage paged parallel eeproms at28lv010 0395c?peepr?04/05
2 0395c?peepr?04/05 at28lv010 2.1 32-lead plcc top view 2.2 32-lead pdip top view 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a12 a15 a16 dc vcc we nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we nc a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 2.3 32-lead tsop top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 nc we vcc nc a16 a15 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 2. pin configurations pin name function a0 - a16 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc don?t connect
3 0395c?peepr?04/05 at28lv010 3. block diagram 4. device operation 4.1 read the at28lv010 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention in their system. 4.2 write the write operation of the at28lv010 allows 1 to 128 bytes of data to be written into the device during a single internal programming period. each write operation must be preceded by the software data protection (sdp) command sequence. this sequence is a series of three unique write command operations that enable the internal write circuitry. the command sequence and the data to be written must conform to the software protected write cycle timing. addresses are latched on the falling edge of we or ce , whichever occurs last and data is latched on the rising edge of we or ce , whichever occurs first. each successive byte must be written within 150 s (t blc ) of the previous byte. if the t blc limit is exceeded the at28lv010 will cease accepting data and commence the internal programming operation. if more than one data byte is to be written during a single programming operation, they must reside on the same page as defined by the state of the a7 - a16 inputs. for each we high to low transition during the page write operation, a7 - a16 must be the same. the a0 to a6 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
4 0395c?peepr?04/05 at28lv010 4.3 data polling the at28lv010 features data polling to indicate the end of a write cycle. during a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle. 4.4 toggle bit in addition to data polling the at28lv010 provides another method for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. 4.5 data protection if precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4.5.1 hardware protection hardware features protect against inadvertent writes to the at28lv010 in the following ways: (a) v cc power-on delay ? once v cc has reached 2.0v (typical) the device will automatically time out 5 ms (typical) before allowing a write; (b) write inhibit ? holding any one of oe low, ce high or we high inhibits write cycles; and (c) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. 4.5.2 software data protection the at28lv010 incorporates the industry standard software data protection (sdp) function. unlike standard 5-volt only eeprom?s, the at28lv010 has sdp enabled at all times. there- fore, all write operations must be preceded by the sdp command sequence. the data in the 3-byte command sequence is not written to the device; the addresses in the command sequence can be utilized just like any other location in the device. any attempt to write to the device without the 3-byte sequence will start the internal timers. no data will be written to the device. however, for the duration of t wc , read operations will effectively be poll- ing operations.
5 0395c?peepr?04/05 at28lv010 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 5. dc and ac operating range at28lv010-20 at28lv010-25 operating temperature (case) com. 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c automotive -40c - 125c v cc power supply 3.3v 5% 3.3v 10% 6. operating modes mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) xhigh z write inhibit x x v ih write inhibit x v il x output disable x v ih xhigh z 7. absolute maximum ratings* temperature under bias................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ...................................-0.6v to +13.5v 8. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 1a i lo output leakage current v i/o = 0v to v cc 1a i sb v cc standby current cmos ce = v cc - 0.3v to v cc + 1v com. 20 a ind. 50 a i cc v cc active current f = 5 mhz; i out = 0 ma; v cc = 3.6v 15 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma; v cc = 3.0v 0.45 v v oh output high voltage i oh = -100 a; v cc = 3.0v 2.4 v
6 0395c?peepr?04/05 at28lv010 10. ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. 9. ac read characteristics symbol parameter at28lv010-20 at28lv010-25 units min max min max t acc address to output delay 200 250 ns t ce (1) ce to output delay 200 250 ns t oe (2) oe to output delay 0 80 0 100 ns t df (3)(4) ce or oe to output float 0 55 0 60 ns t oh output hold from oe , ce or address, whichever occurred first 00ns
7 0395c?peepr?04/05 at28lv010 11. input test waveforms and measurement level 12. output test load note: 1. this parameter is characterized and is not 100% tested. t r , t f < 5 ns 13. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
8 0395c?peepr?04/05 at28lv010 note: 1. all write operations must be preceded by the sdp command sequence. 15. ac write waveforms 15.1 we controlled 15.2 ce controlled 14. ac write characteristics (1) symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 100 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce ) 200 ns t ds data set-up time 100 ns t dh , t oeh data, oe hold time 10 ns
9 0395c?peepr?04/05 at28lv010 17. programming algorithm notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. data protect state will be re-activated at the end of program cycle. 3. 1 to 128 bytes of data are loaded. 18. software protected program cycle waveforms (1)(2)(3) notes: 1. a0 - a14 must conform to the addressing sequence for the first three bytes as shown above. 2. after the command sequence has been issued and a page write operation follows, the page address inputs (a7 - a16) must be the same for each high to low transition of we (or ce ). 3. oe must be high only when we and ce are both low. 16. software protected write characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 100 ns t ds data set-up time 100 ns t dh data hold time 10 ns t wp write pulse width 200 ns t blc byte load cycle time 150 s t wph write pulse width high 100 ns load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (3) load last byte to last address (3) enter data protect state writes enabled (2)
10 0395c?peepr?04/05 at28lv010 notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics 20. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics 22. toggle bit waveforms notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. 19. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns 21. toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
11 0395c?peepr?04/05 at28lv010 23. ordering information (1) note: 1. see ?valid part numbers? below. 23.1 standard package t acc (ns) i cc (ma) ordering code package operation range active standby 200 15 0.02 at28lv010-20jc at28lv010-20pc at28lv010-20tc 32j 32p6 32t commercial (0 to 70 c) 15 0.05 at28lv010-20ji at28lv010-20pi at28lv010-20ti 32j 32p6 32t industrial (-40 to 85 c) 15 0.05 at28lv010-20ta 32t automotive (-40 to 125 c) 250 15 0.02 at28lv010-25jc at28lv010-25pc at28lv010-25tc 32j 32p6 32t commercial (0 to 70 c) 15 0.05 at28lv010-25ji at28lv010-25pi at28lv010-25ti 32j 32p6 32t industrial (-40 to 85 c) 23.2 green package option (pb/halide-free) t acc (ns) i cc (ma) ordering code package operation range active standby 200 15 0.05 at28lv010-20ju at28lv010-20tu 32j 32t industrial (-40 to 85 c) package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 32p6 32-lead, 0.600? wide, plastic dual inline package (pdip) 32t 32-lead, plastic thin small outline package (tsop) 24. valid part numbers the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28lv010 20 jc, ji, ju, pc, pi, tc, ti, tu at28lv010 25 jc, ji, pc, pi, tc, ti 25. die products reference section: parallel eeprom die products
12 0395c?peepr?04/05 at28lv010 26. packaging information 26.1 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
13 0395c?peepr?04/05 at28lv010 26.2 32p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32p6 , 32-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 32p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 41.783 ? 42.291 note 1 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 1 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
14 0395c?peepr?04/05 at28lv010 26.3 32t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32t , 32-lead (8 x 20 mm package) plastic thin small outline package, type i (tsop) b 32t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation bd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
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